TY  - DATA
AU  - Ciletti,Michael D.
TI  - Silos 2001, Verilog HDL logic simulator for Advanced digital design with the Verilog HDL
SN  - 0130891614
PY  - 2003///
CY  - Upper Saddle River, N.J.
PB  - Prentice Hall
KW  - Digital electronics
KW  - Logic circuits
KW  - Computer-aided design
KW  - Verilog (Computer hardware description language)
N1  - Includes book : "Advanced digital design with the Verilog HDL / by Michael D. Ciletti (AUA-PL-0017215)"
UR  - http://www.simucad.com
ER  -